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cpu.h
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1 /*
2 *********************************************************************************************************
3 * uC/CPU
4 * CPU CONFIGURATION & PORT LAYER
5 *
6 * (c) Copyright 2004-2009; Micrium, Inc.; Weston, FL
7 *
8 * All rights reserved. Protected by international copyright laws.
9 *
10 * uC/CPU is provided in source form for FREE evaluation, for educational
11 * use or peaceful research. If you plan on using uC/CPU in a commercial
12 * product you need to contact Micrium to properly license its use in your
13 * product. We provide ALL the source code for your convenience and to
14 * help you experience uC/CPU. The fact that the source code is provided
15 * does NOT mean that you can use it without paying a licensing fee.
16 *
17 * Knowledge of the source code may NOT be used to develop a similar product.
18 *
19 * Please help us continue to provide the Embedded community with the finest
20 * software available. Your honesty is greatly appreciated.
21 *********************************************************************************************************
22 */
23 
24 /*
25 *********************************************************************************************************
26 *
27 * CPU PORT FILE
28 *
29 * ARM-Cortex-M3
30 * IAR C Compiler
31 *
32 * Filename : cpu.h
33 * Version : V1.23
34 * Programmer(s) : JJL
35 * BAN
36 *********************************************************************************************************
37 */
38 
39 
40 /*
41 *********************************************************************************************************
42 * MODULE
43 *********************************************************************************************************
44 */
45 
46 #ifndef CPU_MODULE_PRESENT
47 #define CPU_MODULE_PRESENT
48 
49 
50 /*
51 *********************************************************************************************************
52 * CPU INCLUDE FILES
53 *
54 * Note(s) : (1) The following CPU files are located in the following directories :
55 *
56 * (a) <Your Product Application>\cpu_cfg.h
57 *
58 * (b) <CPU-Compiler Directory>\cpu_def.h
59 *
60 * (c) <CPU-Compiler Directory><cpu><compiler>\cpu*.*
61 *
62 * where
63 * <Your Product Application> directory path for Your Product's Application
64 * <CPU-Compiler Directory> directory path for common CPU-compiler software
65 * <cpu> directory name for specific CPU
66 * <compiler> directory name for specific compiler
67 *
68 * (2) Compiler MUST be configured to include the '<CPU-Compiler Directory>\' directory & the
69 * specific CPU-compiler directory as additional include path directories.
70 *
71 * (3) Since NO custom library modules are included, 'cpu.h' may ONLY use configurations from
72 * CPU configuration file 'cpu_cfg.h' that do NOT reference any custom library definitions.
73 *
74 * In other words, 'cpu.h' may use 'cpu_cfg.h' configurations that are #define'd to numeric
75 * constants or to NULL (i.e. NULL-valued #define's); but may NOT use configurations to
76 * custom library #define's (e.g. DEF_DISABLED or DEF_ENABLED).
77 *********************************************************************************************************
78 */
79 
80 #include <cpu_def.h>
81 #include <cpu_cfg.h> /* See Note #3. */
82 
83 
84 /*$PAGE*/
85 /*
86 *********************************************************************************************************
87 * CONFIGURE STANDARD DATA TYPES
88 *
89 * Note(s) : (1) Configure standard data types according to CPU-/compiler-specifications.
90 *
91 * (2) (a) (1) 'CPU_FNCT_VOID' data type defined to replace the commonly-used function pointer
92 * data type of a pointer to a function which returns void & has no arguments.
93 *
94 * (2) Example function pointer usage :
95 *
96 * CPU_FNCT_VOID FnctName;
97 *
98 * FnctName();
99 *
100 * (b) (1) 'CPU_FNCT_PTR' data type defined to replace the commonly-used function pointer
101 * data type of a pointer to a function which returns void & has a single void
102 * pointer argument.
103 *
104 * (2) Example function pointer usage :
105 *
106 * CPU_FNCT_PTR FnctName;
107 * void *p_obj
108 *
109 * FnctName(p_obj);
110 *********************************************************************************************************
111 */
112 
113 typedef void CPU_VOID;
114 typedef char CPU_CHAR; /* 8-bit character */
115 typedef unsigned char CPU_BOOLEAN; /* 8-bit boolean or logical */
116 typedef unsigned char CPU_INT08U; /* 8-bit unsigned integer */
117 typedef signed char CPU_INT08S; /* 8-bit signed integer */
118 typedef unsigned short CPU_INT16U; /* 16-bit unsigned integer */
119 typedef signed short CPU_INT16S; /* 16-bit signed integer */
120 typedef unsigned int CPU_INT32U; /* 32-bit unsigned integer */
121 typedef signed int CPU_INT32S; /* 32-bit signed integer */
122 typedef unsigned long long CPU_INT64U; /* 64-bit unsigned integer */
123 typedef signed long long CPU_INT64S; /* 64-bit signed integer */
124 
125 typedef float CPU_FP32; /* 32-bit floating point */
126 typedef double CPU_FP64; /* 64-bit floating point */
127 
128 
129 typedef volatile CPU_INT08U CPU_REG08; /* 8-bit register */
130 typedef volatile CPU_INT16U CPU_REG16; /* 16-bit register */
131 typedef volatile CPU_INT32U CPU_REG32; /* 32-bit register */
132 typedef volatile CPU_INT64U CPU_REG64; /* 64-bit register */
133 
134 
135 typedef void (*CPU_FNCT_VOID)(void); /* See Note #2a. */
136 typedef void (*CPU_FNCT_PTR )(void *); /* See Note #2b. */
137 
138 
139 /*$PAGE*/
140 /*
141 *********************************************************************************************************
142 * CPU WORD CONFIGURATION
143 *
144 * Note(s) : (1) Configure CPU_CFG_ADDR_SIZE & CPU_CFG_DATA_SIZE with CPU's word sizes :
145 *
146 * CPU_WORD_SIZE_08 8-bit word size
147 * CPU_WORD_SIZE_16 16-bit word size
148 * CPU_WORD_SIZE_32 32-bit word size
149 * CPU_WORD_SIZE_64 64-bit word size See Note #1a
150 *
151 * (a) 64-bit word size NOT currently supported.
152 *
153 * (2) Configure CPU_CFG_ENDIAN_TYPE with CPU's data-word-memory order :
154 *
155 * (a) CPU_ENDIAN_TYPE_BIG Big- endian word order (CPU words' most significant
156 * octet @ lowest memory address)
157 * (b) CPU_ENDIAN_TYPE_LITTLE Little-endian word order (CPU words' least significant
158 * octet @ lowest memory address)
159 *********************************************************************************************************
160 */
161 
162  /* Define CPU word sizes (see Note #1) : */
163 #define CPU_CFG_ADDR_SIZE CPU_WORD_SIZE_32 /* Defines CPU address word size (in octets). */
164 #define CPU_CFG_DATA_SIZE CPU_WORD_SIZE_32 /* Defines CPU data word size (in octets). */
165 
166 #define CPU_CFG_ENDIAN_TYPE CPU_ENDIAN_TYPE_LITTLE /* Defines CPU data word-memory order (see Note #2). */
167 
168 
169 /*
170 *********************************************************************************************************
171 * CONFIGURE CPU ADDRESS & DATA TYPES
172 *********************************************************************************************************
173 */
174 
175  /* CPU address type based on address bus size. */
176 #if (CPU_CFG_ADDR_SIZE == CPU_WORD_SIZE_32)
177 typedef CPU_INT32U CPU_ADDR;
178 #elif (CPU_CFG_ADDR_SIZE == CPU_WORD_SIZE_16)
179 typedef CPU_INT16U CPU_ADDR;
180 #else
181 typedef CPU_INT08U CPU_ADDR;
182 #endif
183 
184  /* CPU data type based on data bus size. */
185 #if (CPU_CFG_DATA_SIZE == CPU_WORD_SIZE_32)
186 typedef CPU_INT32U CPU_DATA;
187 #elif (CPU_CFG_DATA_SIZE == CPU_WORD_SIZE_16)
188 typedef CPU_INT16U CPU_DATA;
189 #else
190 typedef CPU_INT08U CPU_DATA;
191 #endif
192 
193 
194 typedef CPU_DATA CPU_ALIGN; /* Defines CPU data-word-alignment size. */
195 typedef CPU_ADDR CPU_SIZE_T; /* Defines CPU standard 'size_t' size. */
196 
197 
198 /*
199 *********************************************************************************************************
200 * CPU STACK CONFIGURATION
201 *
202 * Note(s) : (1) Configure CPU_CFG_STK_GROWTH in 'cpu.h' with CPU's stack growth order :
203 *
204 * (a) CPU_STK_GROWTH_LO_TO_HI CPU stack pointer increments to the next higher stack
205 * memory address after data is pushed onto the stack
206 * (b) CPU_STK_GROWTH_HI_TO_LO CPU stack pointer decrements to the next lower stack
207 * memory address after data is pushed onto the stack
208 *********************************************************************************************************
209 */
210 
211 #define CPU_CFG_STK_GROWTH CPU_STK_GROWTH_HI_TO_LO /* Defines CPU stack growth order (see Note #1). */
212 
213 typedef CPU_INT32U CPU_STK; /* Defines CPU stack word size (in octets). */
214 
215 
216 /*$PAGE*/
217 /*
218 *********************************************************************************************************
219 * CRITICAL SECTION CONFIGURATION
220 *
221 * Note(s) : (1) Configure CPU_CFG_CRITICAL_METHOD with CPU's/compiler's critical section method :
222 *
223 * Enter/Exit critical sections by ...
224 *
225 * CPU_CRITICAL_METHOD_INT_DIS_EN Disable/Enable interrupts
226 * CPU_CRITICAL_METHOD_STATUS_STK Push/Pop interrupt status onto stack
227 * CPU_CRITICAL_METHOD_STATUS_LOCAL Save/Restore interrupt status to local variable
228 *
229 * (a) CPU_CRITICAL_METHOD_INT_DIS_EN is NOT a preferred method since it does NOT support
230 * multiple levels of interrupts. However, with some CPUs/compilers, this is the only
231 * available method.
232 *
233 * (b) CPU_CRITICAL_METHOD_STATUS_STK is one preferred method since it supports multiple
234 * levels of interrupts. However, this method assumes that the compiler provides C-level
235 * &/or assembly-level functionality for the following :
236 *
237 * ENTER CRITICAL SECTION :
238 * (1) Push/save interrupt status onto a local stack
239 * (2) Disable interrupts
240 *
241 * EXIT CRITICAL SECTION :
242 * (3) Pop/restore interrupt status from a local stack
243 *
244 * (c) CPU_CRITICAL_METHOD_STATUS_LOCAL is one preferred method since it supports multiple
245 * levels of interrupts. However, this method assumes that the compiler provides C-level
246 * &/or assembly-level functionality for the following :
247 *
248 * ENTER CRITICAL SECTION :
249 * (1) Save interrupt status into a local variable
250 * (2) Disable interrupts
251 *
252 * EXIT CRITICAL SECTION :
253 * (3) Restore interrupt status from a local variable
254 *
255 * (2) Critical section macro's most likely require inline assembly. If the compiler does NOT
256 * allow inline assembly in C source files, critical section macro's MUST call an assembly
257 * subroutine defined in a 'cpu_a.asm' file located in the following software directory :
258 *
259 * <CPU-Compiler Directory><cpu><compiler>\
260 *
261 * where
262 * <CPU-Compiler Directory> directory path for common CPU-compiler software
263 * <cpu> directory name for specific CPU
264 * <compiler> directory name for specific compiler
265 *
266 * (3) (a) To save/restore interrupt status, a local variable 'cpu_sr' of type 'CPU_SR' MAY need
267 * to be declared (e.g. if 'CPU_CRITICAL_METHOD_STATUS_LOCAL' method is configured).
268 *
269 * (1) 'cpu_sr' local variable SHOULD be declared via the CPU_SR_ALLOC() macro which, if
270 * used, MUST be declared following ALL other local variables.
271 *
272 * (b) Configure 'CPU_SR' data type with the appropriate-sized CPU data type large enough to
273 * completely store the CPU's/compiler's status word.
274 *********************************************************************************************************
275 */
276 /*$PAGE*/
277  /* Configure CPU critical method (see Note #1) : */
278 #define CPU_CFG_CRITICAL_METHOD CPU_CRITICAL_METHOD_STATUS_LOCAL
279 
280 typedef CPU_INT32U CPU_SR; /* Defines CPU status register size (see Note #3b). */
281 
282  /* Allocates CPU status register word (see Note #3a). */
283 #if (CPU_CFG_CRITICAL_METHOD == CPU_CRITICAL_METHOD_STATUS_LOCAL)
284 #define CPU_SR_ALLOC() CPU_SR cpu_sr = (CPU_SR)0;
285 #else
286 #define CPU_SR_ALLOC()
287 #endif
288 
289 
290 
291 #define CPU_INT_DIS() { cpu_sr = CPU_SR_Save(); } /* Save CPU status word & disable interrupts. */
292 #define CPU_INT_EN() { CPU_SR_Restore(cpu_sr); } /* Restore CPU status word. */
293 
294 
295 #ifdef CPU_CFG_INT_DIS_MEAS_EN
296  /* Disable interrupts, ... */
297  /* ... & start interrupts disabled time measurement. */
298 #define CPU_CRITICAL_ENTER() { CPU_INT_DIS(); \
299  CPU_IntDisMeasStart(); }
300  /* Stop & measure interrupts disabled time, ... */
301  /* ... & re-enable interrupts. */
302 #define CPU_CRITICAL_EXIT() { CPU_IntDisMeasStop(); \
303  CPU_INT_EN(); }
304 
305 #else
306 
307 #define CPU_CRITICAL_ENTER() { CPU_INT_DIS(); } /* Disable interrupts. */
308 #define CPU_CRITICAL_EXIT() { CPU_INT_EN(); } /* Re-enable interrupts. */
309 
310 #endif
311 
312 
313 /*$PAGE*/
314 /*
315 *********************************************************************************************************
316 * FUNCTION PROTOTYPES
317 *
318 * Note(s) : (1) CPU_CntLeadZeros() prototyped/defined respectively in :
319 *
320 * (a) 'cpu.h'/'cpu_a.asm', if CPU_CFG_LEAD_ZEROS_ASM_PRESENT #define'd in 'cpu.h'
321 * to enable assembly-version function
322 *
323 * (b) 'cpu_core.h'/'cpu_core.c', if CPU_CFG_LEAD_ZEROS_ASM_PRESENT NOT #define'd in 'cpu.h'
324 * to enable C-source-version function otherwise
325 *
326 * See also 'cpu_core.h FUNCTION PROTOTYPES Note #1'.
327 *********************************************************************************************************
328 */
329 
330 void CPU_IntDis (void);
331 void CPU_IntEn (void);
332 
333 void CPU_IntSrcDis (CPU_INT08U pos);
334 void CPU_IntSrcEn (CPU_INT08U pos);
335 CPU_INT16S CPU_IntSrcPrioGet(CPU_INT08U pos);
336 void CPU_IntSrcPrioSet(CPU_INT08U pos,
337  CPU_INT08U prio);
338 
339 
340 void CPU_WaitForInt (void);
341 void CPU_WaitForExcept(void);
342 
343 
344 CPU_SR CPU_SR_Save (void);
345 void CPU_SR_Restore (CPU_SR cpu_sr);
346 
347 
348 
349 #define CPU_CFG_LEAD_ZEROS_ASM_PRESENT /* See Note #1. */
350 
351 CPU_DATA CPU_CntLeadZeros (CPU_DATA val);
352 CPU_DATA CPU_RevBits (CPU_DATA val);
353 
354 
355 void CPU_BitBandClr (CPU_ADDR addr,
356  CPU_INT08U bit_nbr);
357 void CPU_BitBandSet (CPU_ADDR addr,
358  CPU_INT08U bit_nbr);
359 
360 
361 /*$PAGE*/
362 /*
363 *********************************************************************************************************
364 * INTERRUPT SOURCES
365 *********************************************************************************************************
366 */
367 
368 #define CPU_INT_STK_PTR 0u
369 #define CPU_INT_RESET 1u
370 #define CPU_INT_NMI 2u
371 #define CPU_INT_HFAULT 3u
372 #define CPU_INT_MEM 4u
373 #define CPU_INT_BUSFAULT 5u
374 #define CPU_INT_USAGEFAULT 6u
375 #define CPU_INT_RSVD_07 7u
376 #define CPU_INT_RSVD_08 8u
377 #define CPU_INT_RSVD_09 9u
378 #define CPU_INT_RSVD_10 10u
379 #define CPU_INT_SVCALL 11u
380 #define CPU_INT_DBGMON 12u
381 #define CPU_INT_RSVD_13 13u
382 #define CPU_INT_PENDSV 14u
383 #define CPU_INT_SYSTICK 15u
384 
385 
386 /*
387 *********************************************************************************************************
388 * CPU REGISTERS
389 *********************************************************************************************************
390 */
391 
392 #define CPU_REG_NVIC_NVIC (*((CPU_REG32 *)(0xE000E004))) /* Int Ctrl'er Type Reg. */
393 #define CPU_REG_NVIC_ST_CTRL (*((CPU_REG32 *)(0xE000E010))) /* SysTick Ctrl & Status Reg. */
394 #define CPU_REG_NVIC_ST_RELOAD (*((CPU_REG32 *)(0xE000E014))) /* SysTick Reload Value Reg. */
395 #define CPU_REG_NVIC_ST_CURRENT (*((CPU_REG32 *)(0xE000E018))) /* SysTick Current Value Reg. */
396 #define CPU_REG_NVIC_ST_CAL (*((CPU_REG32 *)(0xE000E01C))) /* SysTick Calibration Value Reg. */
397 
398 #define CPU_REG_NVIC_SETEN(n) (*((CPU_REG32 *)(0xE000E100 + (n) * 4u))) /* IRQ Set En Reg. */
399 #define CPU_REG_NVIC_CLREN(n) (*((CPU_REG32 *)(0xE000E180 + (n) * 4u))) /* IRQ Clr En Reg. */
400 #define CPU_REG_NVIC_SETPEND(n) (*((CPU_REG32 *)(0xE000E200 + (n) * 4u))) /* IRQ Set Pending Reg. */
401 #define CPU_REG_NVIC_CLRPEND(n) (*((CPU_REG32 *)(0xE000E280 + (n) * 4u))) /* IRQ Clr Pending Reg. */
402 #define CPU_REG_NVIC_ACTIVE(n) (*((CPU_REG32 *)(0xE000E300 + (n) * 4u))) /* IRQ Active Reg. */
403 #define CPU_REG_NVIC_PRIO(n) (*((CPU_REG32 *)(0xE000E400 + (n) * 4u))) /* IRQ Prio Reg. */
404 
405 #define CPU_REG_NVIC_CPUID (*((CPU_REG32 *)(0xE000ED00))) /* CPUID Base Reg. */
406 #define CPU_REG_NVIC_ICSR (*((CPU_REG32 *)(0xE000ED04))) /* Int Ctrl State Reg. */
407 #define CPU_REG_NVIC_VTOR (*((CPU_REG32 *)(0xE000ED08))) /* Vect Tbl Offset Reg. */
408 #define CPU_REG_NVIC_AIRCR (*((CPU_REG32 *)(0xE000ED0C))) /* App Int/Reset Ctrl Reg. */
409 #define CPU_REG_NVIC_SCR (*((CPU_REG32 *)(0xE000ED10))) /* System Ctrl Reg. */
410 #define CPU_REG_NVIC_CCR (*((CPU_REG32 *)(0xE000ED14))) /* Cfg Ctrl Reg. */
411 #define CPU_REG_NVIC_SHPRI1 (*((CPU_REG32 *)(0xE000ED18))) /* System Handlers 4 to 7 Prio. */
412 #define CPU_REG_NVIC_SHPRI2 (*((CPU_REG32 *)(0xE000ED1C))) /* System Handlers 8 to 11 Prio. */
413 #define CPU_REG_NVIC_SHPRI3 (*((CPU_REG32 *)(0xE000ED20))) /* System Handlers 12 to 15 Prio. */
414 #define CPU_REG_NVIC_SHCSR (*((CPU_REG32 *)(0xE000ED24))) /* System Handler Ctrl & State Reg. */
415 #define CPU_REG_NVIC_CFSR (*((CPU_REG32 *)(0xE000ED28))) /* Configurable Fault Status Reg. */
416 #define CPU_REG_NVIC_HFSR (*((CPU_REG32 *)(0xE000ED2C))) /* Hard Fault Status Reg. */
417 #define CPU_REG_NVIC_DFSR (*((CPU_REG32 *)(0xE000ED30))) /* Debug Fault Status Reg. */
418 #define CPU_REG_NVIC_MMFAR (*((CPU_REG32 *)(0xE000ED34))) /* Mem Manage Addr Reg. */
419 #define CPU_REG_NVIC_BFAR (*((CPU_REG32 *)(0xE000ED38))) /* Bus Fault Addr Reg. */
420 #define CPU_REG_NVIC_AFSR (*((CPU_REG32 *)(0xE000ED3C))) /* Aux Fault Status Reg. */
421 
422 #define CPU_REG_NVIC_PFR0 (*((CPU_REG32 *)(0xE000ED40))) /* Processor Feature Reg 0. */
423 #define CPU_REG_NVIC_PFR1 (*((CPU_REG32 *)(0xE000ED44))) /* Processor Feature Reg 1. */
424 #define CPU_REG_NVIC_DFR0 (*((CPU_REG32 *)(0xE000ED48))) /* Debug Feature Reg 0. */
425 #define CPU_REG_NVIC_AFR0 (*((CPU_REG32 *)(0xE000ED4C))) /* Aux Feature Reg 0. */
426 #define CPU_REG_NVIC_MMFR0 (*((CPU_REG32 *)(0xE000ED50))) /* Memory Model Feature Reg 0. */
427 #define CPU_REG_NVIC_MMFR1 (*((CPU_REG32 *)(0xE000ED54))) /* Memory Model Feature Reg 1. */
428 #define CPU_REG_NVIC_MMFR2 (*((CPU_REG32 *)(0xE000ED58))) /* Memory Model Feature Reg 2. */
429 #define CPU_REG_NVIC_MMFR3 (*((CPU_REG32 *)(0xE000ED5C))) /* Memory Model Feature Reg 3. */
430 #define CPU_REG_NVIC_ISAFR0 (*((CPU_REG32 *)(0xE000ED60))) /* ISA Feature Reg 0. */
431 #define CPU_REG_NVIC_ISAFR1 (*((CPU_REG32 *)(0xE000ED64))) /* ISA Feature Reg 1. */
432 #define CPU_REG_NVIC_ISAFR2 (*((CPU_REG32 *)(0xE000ED68))) /* ISA Feature Reg 2. */
433 #define CPU_REG_NVIC_ISAFR3 (*((CPU_REG32 *)(0xE000ED6C))) /* ISA Feature Reg 3. */
434 #define CPU_REG_NVIC_ISAFR4 (*((CPU_REG32 *)(0xE000ED70))) /* ISA Feature Reg 4. */
435 #define CPU_REG_NVIC_SW_TRIG (*((CPU_REG32 *)(0xE000EF00))) /* Software Trigger Int Reg. */
436 
437 #define CPU_REG_MPU_TYPE (*((CPU_REG32 *)(0xE000ED90))) /* MPU Type Reg. */
438 #define CPU_REG_MPU_CTRL (*((CPU_REG32 *)(0xE000ED94))) /* MPU Ctrl Reg. */
439 #define CPU_REG_MPU_REG_NBR (*((CPU_REG32 *)(0xE000ED98))) /* MPU Region Nbr Reg. */
440 #define CPU_REG_MPU_REG_BASE (*((CPU_REG32 *)(0xE000ED9C))) /* MPU Region Base Addr Reg. */
441 #define CPU_REG_MPU_REG_ATTR (*((CPU_REG32 *)(0xE000EDA0))) /* MPU Region Attrib & Size Reg. */
442 
443 #define CPU_REG_DBG_CTRL (*((CPU_REG32 *)(0xE000EDF0))) /* Debug Halting Ctrl & Status Reg. */
444 #define CPU_REG_DBG_SELECT (*((CPU_REG32 *)(0xE000EDF4))) /* Debug Core Reg Selector Reg. */
445 #define CPU_REG_DBG_DATA (*((CPU_REG32 *)(0xE000EDF8))) /* Debug Core Reg Data Reg. */
446 #define CPU_REG_DBG_INT (*((CPU_REG32 *)(0xE000EDFC))) /* Debug Except & Monitor Ctrl Reg. */
447 
448 
449 /*$PAGE*/
450 /*
451 *********************************************************************************************************
452 * CPU REGISTER BITS
453 *********************************************************************************************************
454 */
455 
456  /* ---------- SYSTICK CTRL & STATUS REG BITS ---------- */
457 #define CPU_REG_NVIC_ST_CTRL_COUNTFLAG 0x00010000
458 #define CPU_REG_NVIC_ST_CTRL_CLKSOURCE 0x00000004
459 #define CPU_REG_NVIC_ST_CTRL_TICKINT 0x00000002
460 #define CPU_REG_NVIC_ST_CTRL_ENABLE 0x00000001
461 
462 
463  /* -------- SYSTICK CALIBRATION VALUE REG BITS -------- */
464 #define CPU_REG_NVIC_ST_CAL_NOREF 0x80000000
465 #define CPU_REG_NVIC_ST_CAL_SKEW 0x40000000
466 
467  /* -------------- INT CTRL STATE REG BITS ------------- */
468 #define CPU_REG_NVIC_ICSR_NMIPENDSET 0x80000000
469 #define CPU_REG_NVIC_ICSR_PENDSVSET 0x10000000
470 #define CPU_REG_NVIC_ICSR_PENDSVCLR 0x08000000
471 #define CPU_REG_NVIC_ICSR_PENDSTSET 0x04000000
472 #define CPU_REG_NVIC_ICSR_PENDSTCLR 0x02000000
473 #define CPU_REG_NVIC_ICSR_ISRPREEMPT 0x00800000
474 #define CPU_REG_NVIC_ICSR_ISRPENDING 0x00400000
475 #define CPU_REG_NVIC_ICSR_RETTOBASE 0x00000800
476 
477  /* ------------- VECT TBL OFFSET REG BITS ------------- */
478 #define CPU_REG_NVIC_VTOR_TBLBASE 0x20000000
479 
480  /* ------------ APP INT/RESET CTRL REG BITS ----------- */
481 #define CPU_REG_NVIC_AIRCR_ENDIANNESS 0x00008000
482 #define CPU_REG_NVIC_AIRCR_SYSRESETREQ 0x00000004
483 #define CPU_REG_NVIC_AIRCR_VECTCLRACTIVE 0x00000002
484 #define CPU_REG_NVIC_AIRCR_VECTRESET 0x00000001
485 
486  /* --------------- SYSTEM CTRL REG BITS --------------- */
487 #define CPU_REG_NVIC_SCR_SEVONPEND 0x00000010
488 #define CPU_REG_NVIC_SCR_SLEEPDEEP 0x00000004
489 #define CPU_REG_NVIC_SCR_SLEEPONEXIT 0x00000002
490 
491  /* ----------------- CFG CTRL REG BITS ---------------- */
492 #define CPU_REG_NVIC_CCR_STKALIGN 0x00000200
493 #define CPU_REG_NVIC_CCR_BFHFNMIGN 0x00000100
494 #define CPU_REG_NVIC_CCR_DIV_0_TRP 0x00000010
495 #define CPU_REG_NVIC_CCR_UNALIGN_TRP 0x00000008
496 #define CPU_REG_NVIC_CCR_USERSETMPEND 0x00000002
497 #define CPU_REG_NVIC_CCR_NONBASETHRDENA 0x00000001
498 
499  /* ------- SYSTEM HANDLER CTRL & STATE REG BITS ------- */
500 #define CPU_REG_NVIC_SHCSR_USGFAULTENA 0x00040000
501 #define CPU_REG_NVIC_SHCSR_BUSFAULTENA 0x00020000
502 #define CPU_REG_NVIC_SHCSR_MEMFAULTENA 0x00010000
503 #define CPU_REG_NVIC_SHCSR_SVCALLPENDED 0x00008000
504 #define CPU_REG_NVIC_SHCSR_BUSFAULTPENDED 0x00004000
505 #define CPU_REG_NVIC_SHCSR_MEMFAULTPENDED 0x00002000
506 #define CPU_REG_NVIC_SHCSR_USGFAULTPENDED 0x00001000
507 #define CPU_REG_NVIC_SHCSR_SYSTICKACT 0x00000800
508 #define CPU_REG_NVIC_SHCSR_PENDSVACT 0x00000400
509 #define CPU_REG_NVIC_SHCSR_MONITORACT 0x00000100
510 #define CPU_REG_NVIC_SHCSR_SVCALLACT 0x00000080
511 #define CPU_REG_NVIC_SHCSR_USGFAULTACT 0x00000008
512 #define CPU_REG_NVIC_SHCSR_BUSFAULTACT 0x00000002
513 #define CPU_REG_NVIC_SHCSR_MEMFAULTACT 0x00000001
514 
515  /* -------- CONFIGURABLE FAULT STATUS REG BITS -------- */
516 #define CPU_REG_NVIC_CFSR_DIVBYZERO 0x02000000
517 #define CPU_REG_NVIC_CFSR_UNALIGNED 0x01000000
518 #define CPU_REG_NVIC_CFSR_NOCP 0x00080000
519 #define CPU_REG_NVIC_CFSR_INVPC 0x00040000
520 #define CPU_REG_NVIC_CFSR_INVSTATE 0x00020000
521 #define CPU_REG_NVIC_CFSR_UNDEFINSTR 0x00010000
522 #define CPU_REG_NVIC_CFSR_BFARVALID 0x00008000
523 #define CPU_REG_NVIC_CFSR_STKERR 0x00001000
524 #define CPU_REG_NVIC_CFSR_UNSTKERR 0x00000800
525 #define CPU_REG_NVIC_CFSR_IMPRECISERR 0x00000400
526 #define CPU_REG_NVIC_CFSR_PRECISERR 0x00000200
527 #define CPU_REG_NVIC_CFSR_IBUSERR 0x00000100
528 #define CPU_REG_NVIC_CFSR_MMARVALID 0x00000080
529 #define CPU_REG_NVIC_CFSR_MSTKERR 0x00000010
530 #define CPU_REG_NVIC_CFSR_MUNSTKERR 0x00000008
531 #define CPU_REG_NVIC_CFSR_DACCVIOL 0x00000002
532 #define CPU_REG_NVIC_CFSR_IACCVIOL 0x00000001
533 
534  /* ------------ HARD FAULT STATUS REG BITS ------------ */
535 #define CPU_REG_NVIC_HFSR_DEBUGEVT 0x80000000
536 #define CPU_REG_NVIC_HFSR_FORCED 0x40000000
537 #define CPU_REG_NVIC_HFSR_VECTTBL 0x00000002
538 
539  /* ------------ DEBUG FAULT STATUS REG BITS ----------- */
540 #define CPU_REG_NVIC_DFSR_EXTERNAL 0x00000010
541 #define CPU_REG_NVIC_DFSR_VCATCH 0x00000008
542 #define CPU_REG_NVIC_DFSR_DWTTRAP 0x00000004
543 #define CPU_REG_NVIC_DFSR_BKPT 0x00000002
544 #define CPU_REG_NVIC_DFSR_HALTED 0x00000001
545 
546 
547 /*$PAGE*/
548 /*
549 *********************************************************************************************************
550 * CONFIGURATION ERRORS
551 *********************************************************************************************************
552 */
553 
554 #ifndef CPU_CFG_ADDR_SIZE
555 #error "CPU_CFG_ADDR_SIZE not #define'd in 'cpu.h' "
556 #error " [MUST be CPU_WORD_SIZE_08 8-bit alignment]"
557 #error " [ || CPU_WORD_SIZE_16 16-bit alignment]"
558 #error " [ || CPU_WORD_SIZE_32 32-bit alignment]"
559 
560 #elif ((CPU_CFG_ADDR_SIZE != CPU_WORD_SIZE_08) && \
561  (CPU_CFG_ADDR_SIZE != CPU_WORD_SIZE_16) && \
562  (CPU_CFG_ADDR_SIZE != CPU_WORD_SIZE_32))
563 #error "CPU_CFG_ADDR_SIZE illegally #define'd in 'cpu.h' "
564 #error " [MUST be CPU_WORD_SIZE_08 8-bit alignment]"
565 #error " [ || CPU_WORD_SIZE_16 16-bit alignment]"
566 #error " [ || CPU_WORD_SIZE_32 32-bit alignment]"
567 #endif
568 
569 
570 #ifndef CPU_CFG_DATA_SIZE
571 #error "CPU_CFG_DATA_SIZE not #define'd in 'cpu.h' "
572 #error " [MUST be CPU_WORD_SIZE_08 8-bit alignment]"
573 #error " [ || CPU_WORD_SIZE_16 16-bit alignment]"
574 #error " [ || CPU_WORD_SIZE_32 32-bit alignment]"
575 
576 #elif ((CPU_CFG_DATA_SIZE != CPU_WORD_SIZE_08) && \
577  (CPU_CFG_DATA_SIZE != CPU_WORD_SIZE_16) && \
578  (CPU_CFG_DATA_SIZE != CPU_WORD_SIZE_32))
579 #error "CPU_CFG_DATA_SIZE illegally #define'd in 'cpu.h' "
580 #error " [MUST be CPU_WORD_SIZE_08 8-bit alignment]"
581 #error " [ || CPU_WORD_SIZE_16 16-bit alignment]"
582 #error " [ || CPU_WORD_SIZE_32 32-bit alignment]"
583 #endif
584 
585 
586 
587 
588 #ifndef CPU_CFG_ENDIAN_TYPE
589 #error "CPU_CFG_ENDIAN_TYPE not #define'd in 'cpu.h' "
590 #error " [MUST be CPU_ENDIAN_TYPE_BIG ]"
591 #error " [ || CPU_ENDIAN_TYPE_LITTLE]"
592 
593 #elif ((CPU_CFG_ENDIAN_TYPE != CPU_ENDIAN_TYPE_BIG ) && \
594  (CPU_CFG_ENDIAN_TYPE != CPU_ENDIAN_TYPE_LITTLE))
595 #error "CPU_CFG_ENDIAN_TYPE illegally #define'd in 'cpu.h' "
596 #error " [MUST be CPU_ENDIAN_TYPE_BIG ]"
597 #error " [ || CPU_ENDIAN_TYPE_LITTLE]"
598 #endif
599 
600 
601 
602 
603 #ifndef CPU_CFG_STK_GROWTH
604 #error "CPU_CFG_STK_GROWTH not #define'd in 'cpu.h' "
605 #error " [MUST be CPU_STK_GROWTH_LO_TO_HI]"
606 #error " [ || CPU_STK_GROWTH_HI_TO_LO]"
607 
608 #elif ((CPU_CFG_STK_GROWTH != CPU_STK_GROWTH_LO_TO_HI) && \
609  (CPU_CFG_STK_GROWTH != CPU_STK_GROWTH_HI_TO_LO))
610 #error "CPU_CFG_STK_GROWTH illegally #define'd in 'cpu.h' "
611 #error " [MUST be CPU_STK_GROWTH_LO_TO_HI]"
612 #error " [ || CPU_STK_GROWTH_HI_TO_LO]"
613 #endif
614 
615 
616 
617 
618 #ifndef CPU_CFG_CRITICAL_METHOD
619 #error "CPU_CFG_CRITICAL_METHOD not #define'd in 'cpu.h' "
620 #error " [MUST be CPU_CRITICAL_METHOD_INT_DIS_EN ]"
621 #error " [ || CPU_CRITICAL_METHOD_STATUS_STK ]"
622 #error " [ || CPU_CRITICAL_METHOD_STATUS_LOCAL]"
623 
624 #elif ((CPU_CFG_CRITICAL_METHOD != CPU_CRITICAL_METHOD_INT_DIS_EN ) && \
625  (CPU_CFG_CRITICAL_METHOD != CPU_CRITICAL_METHOD_STATUS_STK ) && \
626  (CPU_CFG_CRITICAL_METHOD != CPU_CRITICAL_METHOD_STATUS_LOCAL))
627 #error "CPU_CFG_CRITICAL_METHOD illegally #define'd in 'cpu.h' "
628 #error " [MUST be CPU_CRITICAL_METHOD_INT_DIS_EN ]"
629 #error " [ || CPU_CRITICAL_METHOD_STATUS_STK ]"
630 #error " [ || CPU_CRITICAL_METHOD_STATUS_LOCAL]"
631 #endif
632 
633 
634 /*$PAGE*/
635 /*
636 *********************************************************************************************************
637 * MODULE END
638 *********************************************************************************************************
639 */
640 
641 #endif /* End of CPU module include. */
642