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os_cpu.h
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1 /*
2 *********************************************************************************************************
3 * uC/OS-II
4 * The Real-Time Kernel
5 *
6 *
7 * (c) Copyright 2006, Micrium, Weston, FL
8 * All Rights Reserved
9 *
10 * ARM Cortex-M3 Port
11 *
12 * File : OS_CPU.H
13 * Version : V2.89
14 * By : Jean J. Labrosse
15 * Brian Nagel
16 *
17 * For : ARMv7M Cortex-M3
18 * Mode : Thumb2
19 * Toolchain : IAR EWARM
20 *********************************************************************************************************
21 */
22 
23 #ifndef OS_CPU_H
24 #define OS_CPU_H
25 
26 
27 #ifdef OS_CPU_GLOBALS
28 #define OS_CPU_EXT
29 #else
30 #define OS_CPU_EXT extern
31 #endif
32 
33 /*
34 *********************************************************************************************************
35 * DATA TYPES
36 * (Compiler Specific)
37 *********************************************************************************************************
38 */
39 
40 typedef unsigned char BOOLEAN;
41 typedef unsigned char INT8U; /* Unsigned 8 bit quantity */
42 typedef signed char INT8S; /* Signed 8 bit quantity */
43 typedef unsigned short INT16U; /* Unsigned 16 bit quantity */
44 typedef signed short INT16S; /* Signed 16 bit quantity */
45 typedef unsigned int INT32U; /* Unsigned 32 bit quantity */
46 typedef signed int INT32S; /* Signed 32 bit quantity */
47 typedef float FP32; /* Single precision floating point */
48 typedef double FP64; /* Double precision floating point */
49 
50 typedef unsigned int OS_STK; /* Each stack entry is 32-bit wide */
51 typedef unsigned int OS_CPU_SR; /* Define size of CPU status register (PSR = 32 bits) */
52 
53 /*
54 *********************************************************************************************************
55 * Cortex-M3
56 * Critical Section Management
57 *
58 * Method #1: Disable/Enable interrupts using simple instructions. After critical section, interrupts
59 * will be enabled even if they were disabled before entering the critical section.
60 * NOT IMPLEMENTED
61 *
62 * Method #2: Disable/Enable interrupts by preserving the state of interrupts. In other words, if
63 * interrupts were disabled before entering the critical section, they will be disabled when
64 * leaving the critical section.
65 * NOT IMPLEMENTED
66 *
67 * Method #3: Disable/Enable interrupts by preserving the state of interrupts. Generally speaking you
68 * would store the state of the interrupt disable flag in the local variable 'cpu_sr' and then
69 * disable interrupts. 'cpu_sr' is allocated in all of uC/OS-II's functions that need to
70 * disable interrupts. You would restore the interrupt disable state by copying back 'cpu_sr'
71 * into the CPU's status register.
72 *********************************************************************************************************
73 */
74 
75 #define OS_CRITICAL_METHOD 3u
76 
77 #if OS_CRITICAL_METHOD == 3u
78 #define OS_ENTER_CRITICAL() {cpu_sr = OS_CPU_SR_Save();}
79 #define OS_EXIT_CRITICAL() {OS_CPU_SR_Restore(cpu_sr);}
80 #endif
81 
82 /*
83 *********************************************************************************************************
84 * Cortex-M3 Miscellaneous
85 *********************************************************************************************************
86 */
87 
88 #define OS_STK_GROWTH 1u /* Stack grows from HIGH to LOW memory on ARM */
89 
90 #define OS_TASK_SW() OSCtxSw()
91 
92 /*
93 *********************************************************************************************************
94 * PROTOTYPES
95 *********************************************************************************************************
96 */
97 
98 #if OS_CRITICAL_METHOD == 3u /* See OS_CPU_A.ASM */
99 OS_CPU_SR OS_CPU_SR_Save(void);
100 void OS_CPU_SR_Restore(OS_CPU_SR cpu_sr);
101 #endif
102 
103 void OSCtxSw(void);
104 void OSIntCtxSw(void);
105 void OSStartHighRdy(void);
106 
107 void OS_CPU_PendSVHandler(void);
108 
109  /* See OS_CPU_C.C */
110 void OS_CPU_SysTickHandler(void);
111 void OS_CPU_SysTickInit(INT32U cnts);
112 #endif