UCOS_TI_LM3S_Keil
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宏定义 | 函数
cpu_c_Ports.c 文件参考
#include <cpu.h>
#include <cpu_core.h>
#include <lib_def.h>
cpu_c_Ports.c 的引用(Include)关系图:

浏览源代码.

宏定义

#define CPU_INT_SRC_POS_MAX   ((((CPU_REG_NVIC_NVIC + 1) & 0x1F) * 32) + 16)
 
#define CPU_BIT_BAND_SRAM_REG_LO   0x20000000
 
#define CPU_BIT_BAND_SRAM_REG_HI   0x200FFFFF
 
#define CPU_BIT_BAND_SRAM_BASE   0x22000000
 
#define CPU_BIT_BAND_PERIPH_REG_LO   0x40000000
 
#define CPU_BIT_BAND_PERIPH_REG_HI   0x400FFFFF
 
#define CPU_BIT_BAND_PERIPH_BASE   0x42000000
 

函数

void CPU_BitBandClr (CPU_ADDR addr, CPU_INT08U bit_nbr)
 
void CPU_BitBandSet (CPU_ADDR addr, CPU_INT08U bit_nbr)
 
void CPU_IntSrcDis (CPU_INT08U pos)
 
void CPU_IntSrcEn (CPU_INT08U pos)
 
void CPU_IntSrcPrioSet (CPU_INT08U pos, CPU_INT08U prio)
 
CPU_INT16S CPU_IntSrcPrioGet (CPU_INT08U pos)
 

宏定义说明

#define CPU_INT_SRC_POS_MAX   ((((CPU_REG_NVIC_NVIC + 1) & 0x1F) * 32) + 16)

在文件 cpu_c_Ports.c 第 59 行定义.

参考自 CPU_IntSrcDis(), CPU_IntSrcEn(), CPU_IntSrcPrioGet() , 以及 CPU_IntSrcPrioSet().

#define CPU_BIT_BAND_SRAM_REG_LO   0x20000000

在文件 cpu_c_Ports.c 第 61 行定义.

参考自 CPU_BitBandClr() , 以及 CPU_BitBandSet().

#define CPU_BIT_BAND_SRAM_REG_HI   0x200FFFFF

在文件 cpu_c_Ports.c 第 62 行定义.

参考自 CPU_BitBandClr() , 以及 CPU_BitBandSet().

#define CPU_BIT_BAND_SRAM_BASE   0x22000000

在文件 cpu_c_Ports.c 第 63 行定义.

参考自 CPU_BitBandClr() , 以及 CPU_BitBandSet().

#define CPU_BIT_BAND_PERIPH_REG_LO   0x40000000

在文件 cpu_c_Ports.c 第 66 行定义.

参考自 CPU_BitBandClr() , 以及 CPU_BitBandSet().

#define CPU_BIT_BAND_PERIPH_REG_HI   0x400FFFFF

在文件 cpu_c_Ports.c 第 67 行定义.

参考自 CPU_BitBandClr() , 以及 CPU_BitBandSet().

#define CPU_BIT_BAND_PERIPH_BASE   0x42000000

在文件 cpu_c_Ports.c 第 68 行定义.

参考自 CPU_BitBandClr() , 以及 CPU_BitBandSet().

函数说明

void CPU_BitBandClr ( CPU_ADDR  addr,
CPU_INT08U  bit_nbr 
)

在文件 cpu_c_Ports.c 第 132 行定义.

参考 CPU_BIT_BAND_PERIPH_BASE, CPU_BIT_BAND_PERIPH_REG_HI, CPU_BIT_BAND_PERIPH_REG_LO, CPU_BIT_BAND_SRAM_BASE, CPU_BIT_BAND_SRAM_REG_HI , 以及 CPU_BIT_BAND_SRAM_REG_LO.

134 {
135  CPU_ADDR bit_word_off;
136  CPU_ADDR bit_word_addr;
137 
138 
139  if ((addr >= CPU_BIT_BAND_SRAM_REG_LO) &&
140  (addr <= CPU_BIT_BAND_SRAM_REG_HI)) {
141  bit_word_off = ((addr - CPU_BIT_BAND_SRAM_REG_LO ) * 32) + (bit_nbr * 4);
142  bit_word_addr = CPU_BIT_BAND_SRAM_BASE + bit_word_off;
143 
144  *(volatile CPU_INT32U *)(bit_word_addr) = 0;
145 
146  } else if ((addr >= CPU_BIT_BAND_PERIPH_REG_LO) &&
147  (addr <= CPU_BIT_BAND_PERIPH_REG_HI)) {
148  bit_word_off = ((addr - CPU_BIT_BAND_PERIPH_REG_LO) * 32) + (bit_nbr * 4);
149  bit_word_addr = CPU_BIT_BAND_PERIPH_BASE + bit_word_off;
150 
151  *(volatile CPU_INT32U *)(bit_word_addr) = 0;
152  }
153 }
void CPU_BitBandSet ( CPU_ADDR  addr,
CPU_INT08U  bit_nbr 
)

在文件 cpu_c_Ports.c 第 175 行定义.

参考 CPU_BIT_BAND_PERIPH_BASE, CPU_BIT_BAND_PERIPH_REG_HI, CPU_BIT_BAND_PERIPH_REG_LO, CPU_BIT_BAND_SRAM_BASE, CPU_BIT_BAND_SRAM_REG_HI , 以及 CPU_BIT_BAND_SRAM_REG_LO.

177 {
178  CPU_ADDR bit_word_off;
179  CPU_ADDR bit_word_addr;
180 
181 
182  if ((addr >= CPU_BIT_BAND_SRAM_REG_LO) &&
183  (addr <= CPU_BIT_BAND_SRAM_REG_HI)) {
184  bit_word_off = ((addr - CPU_BIT_BAND_SRAM_REG_LO ) * 32) + (bit_nbr * 4);
185  bit_word_addr = CPU_BIT_BAND_SRAM_BASE + bit_word_off;
186 
187  *(volatile CPU_INT32U *)(bit_word_addr) = 1;
188 
189  } else if ((addr >= CPU_BIT_BAND_PERIPH_REG_LO) &&
190  (addr <= CPU_BIT_BAND_PERIPH_REG_HI)) {
191  bit_word_off = ((addr - CPU_BIT_BAND_PERIPH_REG_LO) * 32) + (bit_nbr * 4);
192  bit_word_addr = CPU_BIT_BAND_PERIPH_BASE + bit_word_off;
193 
194  *(volatile CPU_INT32U *)(bit_word_addr) = 1;
195  }
196 }
void CPU_IntSrcDis ( CPU_INT08U  pos)

在文件 cpu_c_Ports.c 第 249 行定义.

参考 CPU_CRITICAL_ENTER, CPU_CRITICAL_EXIT, CPU_INT_BUSFAULT, CPU_INT_DBGMON, CPU_INT_HFAULT, CPU_INT_MEM, CPU_INT_NMI, CPU_INT_PENDSV, CPU_INT_RESET, CPU_INT_RSVD_07, CPU_INT_RSVD_08, CPU_INT_RSVD_09, CPU_INT_RSVD_10, CPU_INT_RSVD_13, CPU_INT_SRC_POS_MAX, CPU_INT_STK_PTR, CPU_INT_SVCALL, CPU_INT_SYSTICK, CPU_INT_USAGEFAULT, CPU_REG_NVIC_CLREN, CPU_REG_NVIC_SHCSR, CPU_REG_NVIC_SHCSR_BUSFAULTENA, CPU_REG_NVIC_SHCSR_MEMFAULTENA, CPU_REG_NVIC_SHCSR_USGFAULTENA, CPU_REG_NVIC_ST_CTRL, CPU_REG_NVIC_ST_CTRL_ENABLE, CPU_SR_ALLOC , 以及 DEF_BIT.

参考自 BSP_IntDis().

250 {
251  CPU_INT08U group;
252  CPU_INT08U pos_max;
253  CPU_INT08U nbr;
254  CPU_SR_ALLOC();
255 
256 
257  switch (pos) {
258  case CPU_INT_STK_PTR: /* ---------------- INVALID OR RESERVED --------------- */
259  case CPU_INT_RSVD_07:
260  case CPU_INT_RSVD_08:
261  case CPU_INT_RSVD_09:
262  case CPU_INT_RSVD_10:
263  case CPU_INT_RSVD_13:
264  break;
265 
266 
267  /* ----------------- SYSTEM EXCEPTIONS ---------------- */
268  case CPU_INT_RESET: /* Reset (see Note #2). */
269  case CPU_INT_NMI: /* Non-maskable interrupt (see Note #2). */
270  case CPU_INT_HFAULT: /* Hard fault (see Note #2). */
271  case CPU_INT_SVCALL: /* SVCall (see Note #2). */
272  case CPU_INT_DBGMON: /* Debug monitor (see Note #2). */
273  case CPU_INT_PENDSV: /* PendSV (see Note #2). */
274  break;
275 
276  case CPU_INT_MEM: /* Memory management. */
277  CPU_CRITICAL_ENTER();
278  CPU_REG_NVIC_SHCSR &= ~CPU_REG_NVIC_SHCSR_MEMFAULTENA;
279  CPU_CRITICAL_EXIT();
280  break;
281 
282  case CPU_INT_BUSFAULT: /* Bus fault. */
283  CPU_CRITICAL_ENTER();
284  CPU_REG_NVIC_SHCSR &= ~CPU_REG_NVIC_SHCSR_BUSFAULTENA;
285  CPU_CRITICAL_EXIT();
286  break;
287 
288  case CPU_INT_USAGEFAULT: /* Usage fault. */
289  CPU_CRITICAL_ENTER();
290  CPU_REG_NVIC_SHCSR &= ~CPU_REG_NVIC_SHCSR_USGFAULTENA;
291  CPU_CRITICAL_EXIT();
292  break;
293 
294  case CPU_INT_SYSTICK: /* SysTick. */
295  CPU_CRITICAL_ENTER();
296  CPU_REG_NVIC_ST_CTRL &= ~CPU_REG_NVIC_ST_CTRL_ENABLE;
297  CPU_CRITICAL_EXIT();
298  break;
299 
300 
301  /* ---------------- EXTERNAL INTERRUPT ---------------- */
302  default:
303  pos_max = CPU_INT_SRC_POS_MAX;
304  if (pos < pos_max) { /* See Note #3. */
305  group = (pos - 16) / 32;
306  nbr = (pos - 16) % 32;
307 
308  CPU_CRITICAL_ENTER();
309  CPU_REG_NVIC_CLREN(group) = DEF_BIT(nbr);
310  CPU_CRITICAL_EXIT();
311  }
312  break;
313  }
314 }

这是这个函数的调用关系图:

void CPU_IntSrcEn ( CPU_INT08U  pos)

在文件 cpu_c_Ports.c 第 338 行定义.

参考 CPU_CRITICAL_ENTER, CPU_CRITICAL_EXIT, CPU_INT_BUSFAULT, CPU_INT_DBGMON, CPU_INT_HFAULT, CPU_INT_MEM, CPU_INT_NMI, CPU_INT_PENDSV, CPU_INT_RESET, CPU_INT_RSVD_07, CPU_INT_RSVD_08, CPU_INT_RSVD_09, CPU_INT_RSVD_10, CPU_INT_RSVD_13, CPU_INT_SRC_POS_MAX, CPU_INT_STK_PTR, CPU_INT_SVCALL, CPU_INT_SYSTICK, CPU_INT_USAGEFAULT, CPU_REG_NVIC_SETEN, CPU_REG_NVIC_SHCSR, CPU_REG_NVIC_SHCSR_BUSFAULTENA, CPU_REG_NVIC_SHCSR_MEMFAULTENA, CPU_REG_NVIC_SHCSR_USGFAULTENA, CPU_REG_NVIC_ST_CTRL, CPU_REG_NVIC_ST_CTRL_ENABLE, CPU_SR_ALLOC , 以及 DEF_BIT.

参考自 BSP_IntEn().

339 {
340  CPU_INT08U group;
341  CPU_INT08U nbr;
342  CPU_INT08U pos_max;
343  CPU_SR_ALLOC();
344 
345 
346  switch (pos) {
347  case CPU_INT_STK_PTR: /* ---------------- INVALID OR RESERVED --------------- */
348  case CPU_INT_RSVD_07:
349  case CPU_INT_RSVD_08:
350  case CPU_INT_RSVD_09:
351  case CPU_INT_RSVD_10:
352  case CPU_INT_RSVD_13:
353  break;
354 
355 
356  /* ----------------- SYSTEM EXCEPTIONS ---------------- */
357  case CPU_INT_RESET: /* Reset (see Note #2). */
358  case CPU_INT_NMI: /* Non-maskable interrupt (see Note #2). */
359  case CPU_INT_HFAULT: /* Hard fault (see Note #2). */
360  case CPU_INT_SVCALL: /* SVCall (see Note #2). */
361  case CPU_INT_DBGMON: /* Debug monitor (see Note #2). */
362  case CPU_INT_PENDSV: /* PendSV (see Note #2). */
363  break;
364 
365  case CPU_INT_MEM: /* Memory management. */
366  CPU_CRITICAL_ENTER();
367  CPU_REG_NVIC_SHCSR |= CPU_REG_NVIC_SHCSR_MEMFAULTENA;
368  CPU_CRITICAL_EXIT();
369  break;
370 
371  case CPU_INT_BUSFAULT: /* Bus fault. */
372  CPU_CRITICAL_ENTER();
373  CPU_REG_NVIC_SHCSR |= CPU_REG_NVIC_SHCSR_BUSFAULTENA;
374  CPU_CRITICAL_EXIT();
375  break;
376 
377  case CPU_INT_USAGEFAULT: /* Usage fault. */
378  CPU_CRITICAL_ENTER();
379  CPU_REG_NVIC_SHCSR |= CPU_REG_NVIC_SHCSR_USGFAULTENA;
380  CPU_CRITICAL_EXIT();
381  break;
382 
383  case CPU_INT_SYSTICK: /* SysTick. */
384  CPU_CRITICAL_ENTER();
385  CPU_REG_NVIC_ST_CTRL |= CPU_REG_NVIC_ST_CTRL_ENABLE;
386  CPU_CRITICAL_EXIT();
387  break;
388 
389 
390  /* ---------------- EXTERNAL INTERRUPT ---------------- */
391  default:
392  pos_max = CPU_INT_SRC_POS_MAX;
393  if (pos < pos_max) { /* See Note #3. */
394  group = (pos - 16) / 32;
395  nbr = (pos - 16) % 32;
396 
397  CPU_CRITICAL_ENTER();
398  CPU_REG_NVIC_SETEN(group) = DEF_BIT(nbr);
399  CPU_CRITICAL_EXIT();
400  }
401  break;
402  }
403 }

这是这个函数的调用关系图:

void CPU_IntSrcPrioSet ( CPU_INT08U  pos,
CPU_INT08U  prio 
)

在文件 cpu_c_Ports.c 第 433 行定义.

参考 CPU_CRITICAL_ENTER, CPU_CRITICAL_EXIT, CPU_INT_BUSFAULT, CPU_INT_DBGMON, CPU_INT_HFAULT, CPU_INT_MEM, CPU_INT_NMI, CPU_INT_PENDSV, CPU_INT_RESET, CPU_INT_RSVD_07, CPU_INT_RSVD_08, CPU_INT_RSVD_09, CPU_INT_RSVD_10, CPU_INT_RSVD_13, CPU_INT_SRC_POS_MAX, CPU_INT_STK_PTR, CPU_INT_SVCALL, CPU_INT_SYSTICK, CPU_INT_USAGEFAULT, CPU_REG_NVIC_PRIO, CPU_REG_NVIC_SHPRI1, CPU_REG_NVIC_SHPRI2, CPU_REG_NVIC_SHPRI3, CPU_RevBits(), CPU_SR_ALLOC, DEF_OCTET_MASK , 以及 DEF_OCTET_NBR_BITS.

参考自 BSP_IntPrioSet().

435 {
436  CPU_INT08U group;
437  CPU_INT08U nbr;
438  CPU_INT08U pos_max;
439  CPU_INT32U prio_32;
440  CPU_INT32U temp;
441  CPU_SR_ALLOC();
442 
443 
444  prio_32 = CPU_RevBits((CPU_INT08U)prio);
445  prio = (CPU_INT08U)(prio_32 >> (3 * DEF_OCTET_NBR_BITS));
446 
447  switch (pos) {
448  case CPU_INT_STK_PTR: /* ---------------- INVALID OR RESERVED --------------- */
449  case CPU_INT_RSVD_07:
450  case CPU_INT_RSVD_08:
451  case CPU_INT_RSVD_09:
452  case CPU_INT_RSVD_10:
453  case CPU_INT_RSVD_13:
454  break;
455 
456 
457  /* ----------------- SYSTEM EXCEPTIONS ---------------- */
458  case CPU_INT_RESET: /* Reset (see Note #2). */
459  case CPU_INT_NMI: /* Non-maskable interrupt (see Note #2). */
460  case CPU_INT_HFAULT: /* Hard fault (see Note #2). */
461  break;
462 
463  case CPU_INT_MEM: /* Memory management. */
464  CPU_CRITICAL_ENTER();
465  temp = CPU_REG_NVIC_SHPRI1;
466  temp &= ~(DEF_OCTET_MASK << (0 * DEF_OCTET_NBR_BITS));
467  temp |= (prio << (0 * DEF_OCTET_NBR_BITS));
468  CPU_REG_NVIC_SHPRI1 = temp;
469  CPU_CRITICAL_EXIT();
470  break;
471 
472  case CPU_INT_BUSFAULT: /* Bus fault. */
473  CPU_CRITICAL_ENTER();
474  temp = CPU_REG_NVIC_SHPRI1;
475  temp &= ~(DEF_OCTET_MASK << (1 * DEF_OCTET_NBR_BITS));
476  temp |= (prio << (1 * DEF_OCTET_NBR_BITS));
477  CPU_REG_NVIC_SHPRI1 = temp;
478  CPU_CRITICAL_EXIT();
479  break;
480 
481  case CPU_INT_USAGEFAULT: /* Usage fault. */
482  CPU_CRITICAL_ENTER();
483  temp = CPU_REG_NVIC_SHPRI1;
484  temp &= ~(DEF_OCTET_MASK << (2 * DEF_OCTET_NBR_BITS));
485  temp |= (prio << (2 * DEF_OCTET_NBR_BITS));
486  CPU_REG_NVIC_SHPRI1 = temp;
487  CPU_CRITICAL_EXIT();
488  break;
489 
490  case CPU_INT_SVCALL: /* SVCall. */
491  CPU_CRITICAL_ENTER();
492  temp = CPU_REG_NVIC_SHPRI2;
493  temp &= ~((CPU_INT32U)DEF_OCTET_MASK << (3 * DEF_OCTET_NBR_BITS));
494  temp |= (prio << (3 * DEF_OCTET_NBR_BITS));
495  CPU_REG_NVIC_SHPRI2 = temp;
496  CPU_CRITICAL_EXIT();
497  break;
498 
499  case CPU_INT_DBGMON: /* Debug monitor. */
500  CPU_CRITICAL_ENTER();
501  temp = CPU_REG_NVIC_SHPRI3;
502  temp &= ~(DEF_OCTET_MASK << (0 * DEF_OCTET_NBR_BITS));
503  temp |= (prio << (0 * DEF_OCTET_NBR_BITS));
504  CPU_REG_NVIC_SHPRI3 = temp;
505  CPU_CRITICAL_EXIT();
506  break;
507 
508  case CPU_INT_PENDSV: /* PendSV. */
509  CPU_CRITICAL_ENTER();
510  temp = CPU_REG_NVIC_SHPRI3;
511  temp &= ~(DEF_OCTET_MASK << (2 * DEF_OCTET_NBR_BITS));
512  temp |= (prio << (2 * DEF_OCTET_NBR_BITS));
513  CPU_REG_NVIC_SHPRI3 = temp;
514  CPU_CRITICAL_EXIT();
515  break;
516 
517  case CPU_INT_SYSTICK: /* SysTick. */
518  CPU_CRITICAL_ENTER();
519  temp = CPU_REG_NVIC_SHPRI3;
520  temp &= ~((CPU_INT32U)DEF_OCTET_MASK << (3 * DEF_OCTET_NBR_BITS));
521  temp |= (prio << (3 * DEF_OCTET_NBR_BITS));
522  CPU_REG_NVIC_SHPRI3 = temp;
523  CPU_CRITICAL_EXIT();
524  break;
525 
526 
527  /* ---------------- EXTERNAL INTERRUPT ---------------- */
528  default:
529  pos_max = CPU_INT_SRC_POS_MAX;
530  if (pos < pos_max) { /* See Note #3. */
531  group = (pos - 16) / 4;
532  nbr = (pos - 16) % 4;
533 
534  CPU_CRITICAL_ENTER();
535  temp = CPU_REG_NVIC_PRIO(group);
536  temp &= ~(DEF_OCTET_MASK << (nbr * DEF_OCTET_NBR_BITS));
537  temp |= (prio << (nbr * DEF_OCTET_NBR_BITS));
538  CPU_REG_NVIC_PRIO(group) = temp;
539  CPU_CRITICAL_EXIT();
540  }
541  break;
542  }
543 }

函数调用图:

这是这个函数的调用关系图:

CPU_INT16S CPU_IntSrcPrioGet ( CPU_INT08U  pos)

在文件 cpu_c_Ports.c 第 568 行定义.

参考 CPU_CRITICAL_ENTER, CPU_CRITICAL_EXIT, CPU_INT_BUSFAULT, CPU_INT_DBGMON, CPU_INT_HFAULT, CPU_INT_MEM, CPU_INT_NMI, CPU_INT_PENDSV, CPU_INT_RESET, CPU_INT_RSVD_07, CPU_INT_RSVD_08, CPU_INT_RSVD_09, CPU_INT_RSVD_10, CPU_INT_RSVD_13, CPU_INT_SRC_POS_MAX, CPU_INT_STK_PTR, CPU_INT_SVCALL, CPU_INT_SYSTICK, CPU_INT_USAGEFAULT, CPU_REG_NVIC_PRIO, CPU_REG_NVIC_SHPRI1, CPU_REG_NVIC_SHPRI2, CPU_REG_NVIC_SHPRI3, CPU_RevBits(), CPU_SR_ALLOC, DEF_INT_16S_MIN_VAL, DEF_OCTET_MASK , 以及 DEF_OCTET_NBR_BITS.

569 {
570  CPU_INT08U group;
571  CPU_INT08U nbr;
572  CPU_INT08U pos_max;
573  CPU_INT16S prio;
574  CPU_INT32U prio_32;
575  CPU_INT32U temp;
576  CPU_SR_ALLOC();
577 
578 
579  switch (pos) {
580  case CPU_INT_STK_PTR: /* ---------------- INVALID OR RESERVED --------------- */
581  case CPU_INT_RSVD_07:
582  case CPU_INT_RSVD_08:
583  case CPU_INT_RSVD_09:
584  case CPU_INT_RSVD_10:
585  case CPU_INT_RSVD_13:
586  prio = DEF_INT_16S_MIN_VAL;
587  break;
588 
589 
590  /* ----------------- SYSTEM EXCEPTIONS ---------------- */
591  case CPU_INT_RESET: /* Reset (see Note #2). */
592  prio = -3;
593  break;
594 
595  case CPU_INT_NMI: /* Non-maskable interrupt (see Note #2). */
596  prio = -2;
597  break;
598 
599  case CPU_INT_HFAULT: /* Hard fault (see Note #2). */
600  prio = -1;
601  break;
602 
603 
604  case CPU_INT_MEM: /* Memory management. */
605  CPU_CRITICAL_ENTER();
606  temp = CPU_REG_NVIC_SHPRI1;
607  prio = (temp >> (0 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
608  CPU_CRITICAL_EXIT();
609  break;
610 
611 
612  case CPU_INT_BUSFAULT: /* Bus fault. */
613  CPU_CRITICAL_ENTER();
614  temp = CPU_REG_NVIC_SHPRI1;
615  prio = (temp >> (1 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
616  CPU_CRITICAL_EXIT();
617  break;
618 
619 
620  case CPU_INT_USAGEFAULT: /* Usage fault. */
621  CPU_CRITICAL_ENTER();
622  temp = CPU_REG_NVIC_SHPRI1;
623  prio = (temp >> (2 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
624  break;
625 
626  case CPU_INT_SVCALL: /* SVCall. */
627  CPU_CRITICAL_ENTER();
628  temp = CPU_REG_NVIC_SHPRI2;
629  prio = (temp >> (3 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
630  CPU_CRITICAL_EXIT();
631  break;
632 
633  case CPU_INT_DBGMON: /* Debug monitor. */
634  CPU_CRITICAL_ENTER();
635  temp = CPU_REG_NVIC_SHPRI3;
636  prio = (temp >> (0 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
637  CPU_CRITICAL_EXIT();
638  break;
639 
640  case CPU_INT_PENDSV: /* PendSV. */
641  CPU_CRITICAL_ENTER();
642  temp = CPU_REG_NVIC_SHPRI3;
643  prio = (temp >> (2 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
644  CPU_CRITICAL_EXIT();
645  break;
646 
647  case CPU_INT_SYSTICK: /* SysTick. */
648  CPU_CRITICAL_ENTER();
649  temp = CPU_REG_NVIC_SHPRI3;
650  prio = (temp >> (3 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
651  CPU_CRITICAL_EXIT();
652  break;
653 
654 
655  /* ---------------- EXTERNAL INTERRUPT ---------------- */
656  default:
657  pos_max = CPU_INT_SRC_POS_MAX;
658  if (pos < pos_max) { /* See Note #3. */
659  group = (pos - 16) / 4;
660  nbr = (pos - 16) % 4;
661 
662  CPU_CRITICAL_ENTER();
663  temp = CPU_REG_NVIC_PRIO(group);
664  CPU_CRITICAL_EXIT();
665 
666  prio = (temp >> (nbr * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
667  } else {
668  prio = DEF_INT_16S_MIN_VAL;
669  }
670  break;
671  }
672 
673  if (prio >= 0) {
674  prio_32 = CPU_RevBits((CPU_INT32U)prio);
675  prio = (CPU_INT16S)(prio_32 >> (3 * DEF_OCTET_NBR_BITS));
676  }
677 
678  return (prio);
679 }

函数调用图: